stack-gate ETOX cell, one of the most popular cell structures for flash memories, is widely programmed by channel hot-electron (CHE) and erased by Fowler-Nordheim (FN) tunneling through the source side or the channel area.
The n-channel ETOX cell is conventionally fabricated using a triple-well process, as shown in FIG. 1. The triple-well structure is typically used to protect cells from noises generated outside the deep n-well by reverse-biasing the deep n-well to p-well junction. The n+ source is typically doubly implanted by As.sup.75 (with a high dose of 3E15/cm.sup.2.about.1E16/cm.sup.2 for the n+ junction) and P.sup.31 (with a lower dose of .about.1E14/cm.sup.2 for the n-junction) so that the source junction can be biased at high voltage (e.g. .about.12 v) during erase operation. The n+ drain is typically implanted by As only with a high dose (.about.1E16/cm.sup.2) and the drain side does not need the lightly-doped-drain (LDD) implant and spacer structure.
The ETOX cell of FIG. 1 is programmed by channel-hot-electrons (CHE). The bias for programming is typically: V.sub.d =7 v, V.sub.cg =9 to 12 v, and V.sub.s =0 v. Under these bias conditions, there is a large channel current (.about.1 mA/cell) for hot electron generation near the channel surface of the drain. Hot electrons are injected into the floating-gate when the oxide energy barrier is overcome and when assisted by the positive control gate bias. After programming, the amount of net electrons on the floating-gate increases, which results in an increase of the cell threshold voltage (V.sub.T). The electrons in the floating-gate will remain for a long time (e.g. 10 years at room temperature), unless intentionally erased.
The cell is erased by Fowler-Nordheim (F-N) tunneling through the source side. The bias during source side erase is typically: V.sub.d.about.0 v or floating, V.sub.cg.about.-5 v to 0 v, and V.sub.s =+9 to +12 v. This establishes a large electrical field (.about.10 Mv/cm) across the tunnel oxide between the floating-gate and source overlap area. Electrons on the floating-gate will tunnel into the source and be removed away.
The read biases of the prior art ETOX-cell are typically: V.sub.d.about.1 v to 2 v, V.sub.cg.about.V.sub.cc, V.sub.s.about.0 v, V.sub.pw.about.0 v, V.sub.dnw =Vcc, and V.sub.sub.about.0 v. The channel may be inverted or not depending on the net electron charge stored on the floating-gate, and results in the on and off of the cell as measured by the read current I.sub.read representing the digital information of "1" or "0" stored in the cell.
One drawback of conventional ETOX cells, as exemplified by FIG. 1, is that the charge on the floating gate may continuously leak away when there are "weak" spots in the tunnel oxide. This is the main limitation that prevents a further decrease in the thickness of the tunnel oxide, which in turn prevents a decrease in the program and erase voltages required. Additionally, the fabrication process for a conventional ETOX cell is more complicated than logic processes, due to the use of high voltage transistors and isolations. Further, the ETOX cell is a single bit memory cell, i.e., only a single bit of data is stored in each ETOX cell.
A prior art multi-bit flash memory cell is exemplified by U.S. Pat. No. 6,011,725 to Eitan. In the '725 patent, a 2-bit cell is formed by replacing the ETOX floating-gate with a charge trapping layer, e.g. nitride or silicon rich oxide (SRO). The charge can be stored locally above the channel near the drain and/or source (referred to as right-bit and left-bit respectively).
The programming of the 2-bits is based on a 2-step procedure using conventional channel-hot-electron (CHE) injection, i.e. CHE programming the drain side (right-bit) by biasing the drain (to 6-7 v) and control-gate (to 10-15 v), then CHE programming the source-side (left-bit) by biasing the source (6-7 v) and control-gate (10-15 v). The read operation is based on a 2-step read, i.e. read the left-bit first by a read bias on the drain (2 v) and control gate (3-5 v), then read the right-bit by biasing the source (2 v) and control gate (3-5 v).
There are several drawbacks of this 2-bit memory cell and its operation. First, the electron trapping layer is still leaky. This is because the charge in the nitride or SRO layer leaks by direct tunneling among traps and/or microscopic silicon islands in the SRO. Note that the SRO is actually oxide with very tiny Si-rich islands (approx. 10 angstroms), which are significantly more conducting than the rest of the oxide. Second, it is difficult to control the trapping density and/or characteristics of the microscopic Si-islands. Third, the 2-step read operation is slow.
In another prior art multi-bit cell, polysilicon spacers are placed on the sides of an n-channel transistor. The oxide underneath the polysilicon spacers is thin and serves as a tunnel oxide for program/erase by F-N tunneling mechanism. The gate oxide is thicker along the channel area. The electron charge is stored in the polysilicon spacers representing 2-bits of digital information. The charge stored in the polysilicon spacer will modify the source/drain resistance measurement relative to a reference resistance. However, this read procedure is slow and complicated.